module uart_byte_tx_2 (
    input clk,
    input[7:0] byte,
    input reset,
    input send_go,//发送触发
    output reg tx,
    output reg tx_led,
    output ready //发送完成
);
//9600    
    
    reg[3:0] sendbits;//十位
    assign ready=(sendbits==10);
    reg [31:0] cont;
    reg [7:0] txbyte;

    parameter contmax = 2812-1;
    always @(posedge clk or negedge reset) begin
        if (reset==0) begin
            cont<=0;
        end else begin
            if (cont==contmax||sendbits==10) begin
                cont<=0;
            end else begin
                cont<=cont+1;
            end
        end
    end

    always @(posedge clk  or negedge reset) begin
        if (reset==0) begin
            sendbits<=10;
            
        end else begin
                if (sendbits==10) begin
                    if (send_go==1) begin                        
                        sendbits<=0;
                    end 
                end else begin
                    if (cont==contmax) begin
                        sendbits<=sendbits+1;
                    end
                    
                end            

        end
    end

    always @(posedge clk or negedge reset) begin
        if (reset==0) begin
            tx<=1;          
            tx_led<=1;  
        end else begin
            case (sendbits)
                0:begin//起始位
                  tx<=0;
                  txbyte<=byte;  
                  tx_led<=0;
                end
                1:begin
                    tx<=txbyte[0];
                end
                2:begin
                    tx<=txbyte[1];
                end
                3:begin
                    tx<=txbyte[2];
                end
                4:begin
                    tx<=txbyte[3];
                end
                5:begin
                    tx<=txbyte[4];
                end
                6:begin
                    tx<=txbyte[5];
                end
                7:begin
                    tx<=txbyte[6];
                end
                8:begin
                    tx<=txbyte[7];
                end
                9:begin//停止位
                    tx<=1;
                end
                10:begin//空闲
                    tx<=1;
                    tx_led<=1;
                end
            endcase
        end
    end

endmodule

